Field of the Invention
The present invention relates to a prober for inspecting electrical characteristics of a plurality of semiconductor devices (chips) formed on a semiconductor wafer, and more particularly to a prober in which an alignment device can be shared by a plurality of measuring units, and to a probe inspection method.
Description of the Related Art
In a semiconductor manufacturing process, there are many processes, and in order to improve quality assurance and yield, various inspections are performed in various manufacturing processes. For example, wafer level inspection is performed in such a manner that, in a stage where a plurality of chips for semiconductor devices are formed on a semiconductor wafer, electrode pads of semiconductor devices on respective chips are connected to a test head, and electric power and test signals are supplied to the electrode pads from the test head. Signals outputted from the semiconductor device are measured by the test head to electrically inspect whether or not the semiconductor devices normally work.
After the wafer level inspection, the wafer is attached to a frame and cut to individual chips by a dicer. Among the cut chips, only the chips which have been confirmed to properly work are respectively packaged in the next assembly process, and hence, the malfunctioning chips are removed from the assembly process. Further, packaged final products are subjected to a shipping inspection.
The wafer level inspection is performed by using a prober in which probes are brought into contact with the electrode pads of each of the chips on the wafer. After the probes are electrically connected to the terminals of the test head, electric power and test signals are supplied to each of the chips from the test head via the probes, and also, the output signals from each of the chips are detected by the test head to measure whether or not the chips normally work.
In the semiconductor manufacturing process, in order to reduce manufacturing cost, the size enlargement of a wafer and further miniaturization (integration) have been advanced, and thereby, the number of chips formed on one wafer has been significantly increased. Accordingly, the time required to inspect one wafer with the prober has been increased, as a result of which the improvement of throughput has been requested. In order to improve the throughput, the multi-probing, in which a number of probes are provided to enable a plurality of chips to be inspected at the same time, has been performed. In recent years, the number of chips to be inspected simultaneously is further increasing and efforts have been made to simultaneously inspect all the chips on one wafer. For this reason, the allowable error in contact alignment between the electrode pad and the probe is reduced, and hence, it is required to improve the position accuracy at the time when the prober is moved.
On the other hand, as the easiest method for increasing the throughput, it is conceivable to increase the number of probers. However, when the number of probers is increased, there arises a problem that the installation area of the probers in the production line is also increased. Further, when the number of probers is increased, the device cost is also increased correspondingly. For this reason, it is required to increase the throughput while suppressing the increase in installation area and the increase in device cost.
Under such background, for example, Japanese Patent Application Laid-Open No. 2010-186998 (hereinafter, referred to as PTL 1) proposes a testing device which has a plurality of measuring units each having a probe card electrically connected to a test head. The testing device is configured such that an alignment device which performs relative alignment between a wafer and the probe card, can be moved among the measuring units.